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Tutorial  
September 26th

Conference Day
September 27th

Location : 690 N. McCarthy Blvd, Milpitas, CA

Interconnected IEEE Standards

Teachers - Adam Cron (Synopsys) and Etienne Racine (Mentor)

There has been a continuous development trend of IEEE Test Standards addressing access to DFT resources inside evolving packaged electronics. This tutorial will address the most popular test access standards and the most salient aspects of each. These include IEEE Stds 1149.1 (package/board connection and beyond) , 1687 (instrument access through 1149.1), 1500 (core wrapping), and P1838 (3DIC test access). These standards can interact with each other and may rely on other IEEE standards to support automated construction, and design and use methodologies which will be addressed by the authors.

9:30 - 10:00am On site Registration (coffee provided)

  • Introductions and Agenda
LUNCH - Free lunch
  • Q&A

~3pm - Class ends

 

 

Location : 690 N. McCarthy Blvd, Milpitas, CA  

AGENDA
9:00 - 9:50 On site Registration (coffee provided)
9:50 - 10:00 Welcomes and introductions

1
0:00 - 10:40 Key Note Address


Ira Leventhal
(Advantest - VP, New Concept Initiatives)

(Click on Ira's picture for Bio)

 


Session 1

10:40 - 11:20 - Presentation 1 - Mike Rodgers (ReachIPs)
         
Title -  Embedded Cache DFT and Test Tradeoffs
11:20 - 12:00 - Presentation 2 - Jon Colburn  (NVidia)
         
Title - DFT Challenges in Large SOC designs

12:00 - 1:00 LUNCH - Free lunch

1:00 1:40 Presentation 3 - Technology Spotlights
                  Mentor Graphics - 20 min
                  SiliconAid - 20 min

Session 2
1:40 2:20 - Presentation 4 - Li-C Wang (UCSB)
        
Title - Intelligent Assistant - A Journey To AI

2:20 3:00 - Presentation 5 - Jeff Hung (Microsoft)
         
Title - DFT Verification with formal methods

3:00 - 3:20 B R E A K
Session 3

3:20 - 4:00 - Presentation 6 - Bill Huynh (Marvell)
        
Title - From Single Die to Multi-Chip Module Testing
4:00 - 4:40 - Presentation 7 - Ashok Mathur (AMD)
        
Title - Mixed Signal DFT challenges and Fault Sim
4
:40 - 5:20 - Presentation 8 - Artie Pennington (HPKD Law)
        
Title - IP Patent discussion and lessons learned

5:20 - 6:30 - Panel Discussion Referee: Jim Johnson
6:30 - 7:30 Happy Hour at TBD